1. Field of the Disclosure
The present disclosure generally relates to electronic devices with various modes of operation and, in one embodiment, to a system and method for automatically selecting between a asynchronous mode or a synchronous mode of operation for an electronic device having an on die termination (ODT) circuit.
2. Brief Description of Related Art
Memory devices are electronic devices that are widely used in many electronic products and computers to store data. A memory device is a semiconductor electronic device that includes a number of memory cells, each cell storing one bit of data. The data stored in the memory cells can be read during a read operation. A memory device may send the data to the data-requesting device in the system (e.g., a processor or a memory controller) via an output driver circuit to maintain requisite signal strength and data integrity.
FIG. 1 is a simplified diagram illustrating a portion of an output driver 10 in an electronic device (e.g., a memory chip) (not shown). The output driver 10 may perform a signal transfer function from an internal or signal-generating part of the electronic device to the external pins on the electronic device, which pins may allow the signal to be propagated to the appropriate device in the system via a signal transfer mechanism (e.g., a bus). In the case of a memory device (not shown), the output driver 10 may transfer the memory's internally-generated data (DQ) signals 18 to data (DQ) pins 20 of the memory chip. It is observed here that although the operation of the output driver 10 is discussed hereinbelow with reference to a memory chip, the discussion may equally apply to such output driver configurations in other non-data signal transfer applications in other electronic devices as well
The output driver unit 10 is shown connected to the data (DQ) pins 20 of the memory chip (not shown). The driver 10 receives the data signals (DQ Out) 18 from the memory cells (not shown) to be output on the DQ pins 20 (e.g., during a memory read operation). In a DDR (Double Data Rate) DRAM (Dynamic Random Access Memory) memory chip, the output driver 10 may also include a set of ODT (On-Die Termination) legs or circuit portion 12 and a set of non-ODT legs or circuit portion 14. The on-chip ODT circuit portion 12 may be used to improve signal integrity in the system. An ODT pin (one of the pins on a memory chip (not shown)) may be provided on the chip to receive an externally-supplied (e.g., by a memory controller (not shown)) ODT enable/disable signal to activate/deactivate the ODT legs 12. Although the ODT circuit 12 in FIG. 1 is shown associated with the DQ pins 20, in practice, corresponding ODT circuits 12 may be provided for any other pins on a memory chip including, for example, the address pins and the control pins (not shown in FIG. 1, but shown in FIG. 2). The ODT circuit 12 may be more prevalent in DDR SDRAMs (Synchronous Dynamic Random Access Memories).
In operation, the ODT circuit 12 provides desired termination impedance to improve signal integrity by controlling reflected noise on the transfer line connecting the memory chip to another processing device, e.g., a memory controller (not shown). In a DDR SDRAM, the termination register (not shown) that was conventionally mounted on a motherboard carrying memory chips is incorporated inside the DDR SDRAM chip to enable or disable the ODT circuit 12 when desired. The termination register may be programmed through an ODT pin (not shown) on the memory chip by an external processor (e.g., a memory controller) to enable/disable the ODT circuit 12. As is known in the art, for example, when two or more memory chips are present in a system, during a memory write operation to one of the chips, the ODT circuit 12 in the other chip (which is not receiving data) is activated to absorb any signal propagations or reflections received on the data lines (or address or control lines, as may be the case) of that “inactive” chip. This selective activation/deactivation of the ODT circuit 12 (e.g., in the memory chip that is not currently sending or receiving data) prevents the “inactive” chip from receiving spurious signals, thereby avoiding data corruption in the chip. The ODT circuit 12 thus improves integrity of signals (e.g., data signals in case of a memory chip) to be provided to external devices via the output driver 10. The non-ODT circuit portion 14 in the output driver 10 may provide routine signal driver functions to data signals as is known in the art.
The output driver 10 may also include an ODT enable/disable logic 16 to provide activation/deactivation of the tuning transistors in the ODT legs 12. A similar control unit (not shown) may also be provided for the activation/deactivation of the non-ODT legs 14. The ODT enable/disable unit 16 may generate a control signal (not shown) that is supplied to the ODT circuit portion 12 to activate or deactivate the ODT legs 12 based on the status of the control signal. The ODT legs 12 as well as the non-ODT legs 14 of the output driver 10 provide necessary signal amplification and buffering to the data signals to be sent from the memory cells (not shown) to the DQ pins 20. However, the ODT legs 12 may additionally provide the ODT functionality when activated. Thus, although the ODT and non-ODT legs may be identically constructed, in operation of the driver 10, the ODT legs 12 may provide output driver function as well as the ODT functionality, whereas the non-ODT legs 14 may just provide the data output driver function (data signal amplification and buffering). Each output of the driver 10 may have an IC (integrated circuit) output pad (not shown) to convey the data signals to the corresponding DQ pins 20 as is known in the art. It is noted here that only a portion of the output driver 10 is shown in FIG. 1 for ease of illustration and clarity. Additional circuit details of FIG. 1 are known in the art and not relevant here and, hence, are not discussed in detail here.
It is observed that in a DDR DRAM chip, even though the external ODT pin (not shown) on the memory chip may receive the ODT enable/disable signal (e.g., from a memory controller (not shown) as noted hereinbefore) in a synchronous manner, the internal operation of the ODT portion 12 can be made synchronous or asynchronous (using the ODT enable/disable logic unit 16) depending on the chip's current mode of operation. For example, when the chip is in a power down mode, the ODT enable/disable logic 16 may detect the power down state and operate the ODT portion 12 in an asynchronous mode even though the external ODT enable/disable signal requires synchronous operation. In the specification that governs the hand-off from when the part (e.g., a memory chip) changes ODT internal operational mode from asynchronous to synchronous and vice versa, the synchronous ODT mode timing is treated as a subset of the asynchronous ODT mode timing. Therefore, it is within the specification for the ODT portion 12 to be operating synchronously internally even when the memory chip is allowed to operate its ODT portion 12 in an asynchronous manner by an external controller (not shown).asynchronous to synchronous and vice versa, the synchronous ODT mode timing is treated as a subset of the asynchronous ODT mode timing. Therefore, it is within the specification for the ODT portion 12 to be operating synchronously internally even when the memory chip is allowed to operate its ODT portion 12 in an asynchronous manner by an external controller (not shown).
The prior art ODT enable/disable logic unit or ODT control unit 16 is a complex circuit involving significant delays in receiving and processing external clock and ODT enable/disable signal. The ODT control unit 16 merely detects (based on appropriate internally-generated clocking signals (not shown) input thereto) the current state of operation of the memory chip and, in response, determines the mode of operation (asynchronous or synchronous) for the ODT legs 12. For example, if various internal clocking signals (derived from the external clock and/or the external ODT enable/disable signal) indicate that the memory chip is entering the power down mode, then the ODT control unit 16 will decide to operate the ODT legs 12 in the asynchronous mode. If the ODT legs 12 are currently operating in the synchronous mode, then the power down indication may require the ODT control unit 16 to switch the ODT mode of operation to the asynchronous mode irrespective of whether the synchronous mode can be continued internally (this is possible, as mentioned before, because the synchronous mode timing specification is a subset of the asynchronous mode timing requirements). The reliance of the ODT control unit 16 on the device's next state (e.g., power down state) may result in wasted clock cycles that may still be available to continue the synchronous ODT mode of operation before the internal clocks are stopped for the power down mode. As is known in the art, there is a delay between a decision is made to enter the power down mode and the internal clocks are finally stopped for the power down mode. Because of the significant delays involved in processing of various clock signals input to the complex prior art ODT control unit 16, it may be easier for the prior art ODT control unit 16 to rely on the current memory state indicated by the clocking signals and switch the ODT mode of operation without regard to the actual status and availability of clock signals internally. Furthermore, the prior art ODT control unit 16 is heavily dependent on the memory device's internal clocking logic. Therefore, when there are design changes in the device clocking logic, all ODT control units 16 on the device (e.g., a memory chip) have to be re-designed/re-configured to accommodate the changes in the clocking logic, which can be time consuming and expensive.
It is therefore desirable to devise an output driver circuit configuration that employs a simple and significantly less complex detector circuit to automatically determine internal ODT mode of operation (asynchronous vs. synchronous) without affecting the speed with which signals may be output from the electronic device and without being affected by the design changes in the device clocking logic. It is further desirable to obtain such an output driver mechanism without significantly adding logic circuitry or requiring more space on the die.